This invention relates to a semiconductor apparatus and, in particular, to a semiconductor apparatus having a preset signal generating circuit for producing a preset signal for use in setting an initial operation of an internal circuit at power on.
Recently, a semiconductor apparatus is developed towards larger-scale integration and higher-speed operation and semiconductor devices used therein are developed towards miniaturization. Following the miniaturization of the semiconductor devices, a power supply voltage of the semiconductor apparatus is lowered. As the power supply voltage is lowered, it is required that each internal circuit of the semiconductor apparatus is supplied with an optimum power supply voltage to perform an optimum operation. By such optimization, large-scale integration and high-speed operation are achieved. For this purpose, the semiconductor apparatus contains an internal power supply voltage generating circuit for generating power supply voltages for various internal circuits. The internal power supply voltage generating circuit generates various internal power supply voltages by stepping up or down an external power supply voltage supplied from the outside.
In the above-mentioned semiconductor apparatus, at power on, an internal circuit preset signal is generated to control rising of a power supply voltage of each of the internal power supply voltage generating circuit and peripheral control circuits supplied with the internal power supply voltages generated by the internal power supply voltage generating circuit. Referring to FIG. 1, the semiconductor apparatus comprises a preset signal (PRESET) generating circuit 11 for generating an internal circuit preset signal PRESET, an internal power supply voltage (VINT) generating circuit 21 for generating an internal power supply voltage VINT, and various peripheral control circuits 22 supplied with the internal power supply voltage VINT and operated by the internal power supply voltage VINT.
The VINT generating circuit 21 and the peripheral control circuits 22 are supplied with a same internal circuit preset signal PRESET1 from the PRESET generating circuit 11. The internal circuit preset signal PRESET1 supplied to the VINT generating circuit 21 at power on serves to accelerate generation of the internal power supply voltage VINT by supplementarily connecting an external power supply VDD to the VINT generating circuit 21. Further, the internal circuit preset signal PRESET 1 supplied to the peripheral control circuits 22 serves to preset internal nodes of the peripheral control circuits 22. A plurality of internal circuit preset signals may be provided for a plurality of VINT generating circuits and a plurality of circuit groups operated by internal power supply voltages generated by the VINT generating circuits, respectively.
In connection with the internal circuit preset signal and power on, several related documents are known. In Japanese Unexamined Patent Application Publication (JP-A) No. 2002-111466 (Patent Document 1), a plurality of power-on reset circuits are provided in correspondence to different power supply voltages supplied from the outside. In Japanese Unexamined Patent Application Publication (JP-A) No. 2003-223783 (Patent Document 2), a power-on reset circuit supplied with an internal power supply voltage Vdd1 produces a plurality of power-on reset signals to reset a plurality of circuits supplied with the internal power supply voltage Vdd1. Japanese Unexamined Patent Application Publication (JP-A) No. 2004-279052 (Patent Document 3) discloses a plurality of power-on reset circuits different in threshold voltage. Japanese Unexamined Patent Application Publication (JP-A) No. 2004-152405 (Patent Document 4) discloses that, in a non-volatile memory having a plurality of chips, timings of power supply to the chips are delayed or shifted so as to prevent an increase of a rising current at power on.
In the above-mentioned Patent Documents 1, 2, and 3, a plurality of power-on reset signals are used. However, the same power-on reset signal is used for a circuit group supplied with one power supply voltage internally generated. In Patent Document 4, timings of supplying the power supply voltage are delayed and no preset operation is performed in synchronism with rising of the power supply voltage. Therefore, the techniques disclosed in the above-mentioned Patent Documents are different from this invention.
In the above-mentioned presetting in FIG. 1 by the internal circuit preset signal, there are several problems. As a first problem, optimum timings of the internal circuit preset signal are different among various internal circuits. This is because timings and periods of operations carried out at power on are different among the respective circuits. For example, in the VINT generating circuit, it is necessary to accelerate generation of the internal power supply voltage VINT by supplementarily connecting the external power supply VDD at power on. The peripheral circuits require timings and periods such that the internal nodes are preset preferably in the state where the internal power supply voltage VINT rises. As a second problem, there is a too small margin to sufficiently perform initial operations at power on by the use of the same internal circuit preset signal. This is because, as the same internal circuit preset signal is used, the various internal circuits perform the initial operations at power on at compromised timings.
As described above, in the semiconductor apparatus lowered in power supply voltage, various internal power supply voltages are used. The VINT generating circuit and the internal circuits using the power supply voltages generated by the VINT generating circuit are different in optimum operation timing at power on. It is necessary to perform presetting at optimum timings.